Synthesis of partition-codec architecture for low power and small area circuit design

Partitioning circuit for low power design in logic level has been proposed as a very effective technique. However, the increased area of latches for duplicated input of multiple partitions always offsets the advantage. In this paper we propose a novel Partition-Codec Architecture to achieve low power and small area. The approach is based on evenly partition the output vectors by the corresponding input variables and re-assigning the output vectors of each partition to minimize the number of input vectors and Hamming distance of each partition, and one of the active decoders returns the value to its original output. Given a combinational circuit described by PLA, we develop a global-encoding algorithm, which consists of partition and re-assigning routines to synthesize the Parition-Codec architecture to achieve low power and small area. Experimental results show that up to 69.5% power reduction, as well as 60.9% area decreased and average 35.7% power saving with 58.4% area reduction are achevable. [ 5 ] . The advantage of this architecture is that it simplifies the precomputation logic as a “decoder”. Nevertheless, the algorithm to select the best input is quite complex and the duplicated input latches is a significant overhead. Ruan, et al. showed that the partitioning circuits more than two-way often lose advantage because of the overhead of duplicated input latches and output multiplexors in area and power [6]. We proposed a bipartition-codec architecture to reduce the power consumption by re-encoding the output of the small subset of the output vectors, however, additional circuit always increases the area and offsets the power saving [7 ] . In this paper, we propose a partition-codec architecture for optimizing the power and area of combinational circuits. The technique is based on evenly partitioning the output vectors by its input variables, where each of them is significantly smaller than the original. Since the output vector number of each partition may be reduced, we develop a global-encoding approach for p‘artitioning and re-assigning the output vectors to minimize the number of input pins of each partition.